1. Field of the Invention
The present invention relates to an insulated gate field effect transistor (FET) and a method of manufacturing the same.
2. Description of the Related Art
At the present time, high integration and an improvement in an operating speed of a semiconductor device are made by miniaturizing a transistor in accordance with the so-called scaling law. When an insulated gate field effect transistor (Metal Insulator Semiconductor FET (MISFET)) is desired to be miniaturized, it is necessary to suppress an influence of the so-called short channel effect. Depletion of a gate electrode as one factor of the short channel effect can not be effectively suppressed as long as the gate electrode is made of a semiconductor material. In order to cope with this situation, it is proposed that the gate electrode is made of a conductive material such as a metal or a metallic compound. With regard to a technique for making a gate electrode of a conductive material, there is proposed a method in which a metallic film, for example, is deposited instead of depositing a polycrystalline silicon film, and the resulting metallic film is patterned similarly to the case of the related art, thereby forming a gate electrode. In addition thereto, there is also proposed a method in which a gate electrode is formed by carrying out the so-called damascene process for filling a conductive material in an opening portion for gate electrode formation. This method, for example, is described in Non-Patent Document 1 of Atsushi Yagishita et al.: “High Performance Metal Gate MOSFETs Fabricated by CMP for 0.1 μm Regime,” International Electron Devices Meeting 1998 Technical Digest pp. 785 to 788 (1998). With the method in which the gate electrode is formed by carrying out the damascene process, a gate insulating film, for example, made of an insulating material (such as a hafnium oxide) having a larger relative permittivity than that of a silicon oxide is formed within an opening portion for gate electrode formation which is formed by removing a dummy gate electrode, and the gate electrode is then formed. As a result, it is possible to improve the characteristics of the insulated gate field effect transistor.
In addition, for the purpose of achieving a balance between optimization of a work function of a gate electrode and a low resistance promotion for the gate electrode, the following method is also proposed. That is to say, when the gate electrode is intended to be formed by carrying out the damascene process, firstly, a thin film first layer (work function controlling layer) made of a conductive material having a suitable work function is formed within an opening portion for gate electrode formation. Next, a second layer made of another conductive material having a smaller resistivity (specific resistance) than that of the conductive material of the first layer is formed, thereby structuring the gate electrode.
An alignment safety margin when contact plugs to be connected to a top surface of a gate electrode and a source/drain region, respectively, are formed in an interlayer insulating layer covering the gate electrode and the source/drain region is reduced along with the miniaturization of the insulated gate field effect transistor. For this reason, it is preferable to simultaneously form those contact plugs by carrying out a series of processes. After formation of an opening portion for contact plug formation having a bottom portion to which the top surface of the gate electrode is exposed, and formation of an opening portion for contact plug formation having a bottom surface to which the source/drain region is exposed, a conductive material such as tungsten is filled in each of those opening portions for contact plug formation, thereby forming the contact plugs. Those opening portions for contact plug formation are formed by utilizing the well known lithography technique and etching technique.
Hereinafter, an outline of a method of forming a gate electrode by carrying out a damascene process in the related art will be described with reference to FIG. 1C, and FIGS. 6A to 6H as schematically partial end views of a silicon semiconductor substrate and the like.
[Process-10]
Firstly, a base 10 including a channel formation region 12, a source/drain region 13, a lower insulating layer 21 made of SiO2, and an opening portion 22 for gate electrode formation formed above the channel formation region 12 is prepared (refer to FIG. 1C).
It is to be noted that a method of manufacturing the base 10 will be described in detail later in Embodiment 1. In addition, in FIG. 1C, reference numeral 11 designates a silicon semiconductor substrate, reference symbol 13A designates a silicide layer formed in a portion overlying the source/drain region 13, and reference numeral 17 designates an offset spacer made of SiN. Also, reference numeral 18 designates a first sidewall made of SiO2, reference numeral 19 designates a second sidewall made of SiN, and reference numeral 20 designates a stress liner layer made of SiN.
[Process-20]
Next, a gate insulating film 630, for example, made of a hafnium oxide, a thin film first layer (work function controlling layer) 631 made of a metallic material (hafnium silicide) for regulating a work function of a gate electrode, and a barrier layer 632A made of TiN are formed in order over the entire surface of the base 10 (refer to FIG. 6A).
[Process-30]
After that time, after a second layer 632 made of tungsten is formed over the entire surface of the base 10 by utilizing a so-called blanket tungsten CVD method, a flattening treatment is carried out by utilizing a CMP method. As a result, the second layer 632, the barrier layer 632A, the first layer 631, and the gate insulating film 630 which overlie a lower insulating layer 21, the offset spacer 17, the first sidewall 18 and the second sidewall 19 are removed (refer to FIG. 6B). In such a manner, a gate electrode 623 can be obtained. Here, the gate electrode 623 is formed above the channel formation region 12 through the gate insulating film 630. Also, the gate electrode 623 is composed of the first layer 631, the barrier layer 632A, and the second layer 632. In addition, the gate insulating film 630 is formed so as to extend from a surface of the semiconductor substrate 11 to a sidewall of the opening portion 22 for gate electrode formation.
[Process-40]
Next, an interlayer insulating layer 34 is formed over the entire surface of the base 10 (refer to FIG. 6C).
[Process-50]
After that, opening portions 35A and 35B for contact plug formation are formed in a portion of the interlayer insulating layer 34 located above the gate electrode 623, and a portion of the lower insulating layer 21 located above the source/drain region 13, respectively. Note that, FIG. 6D shows a state at a time point when formation of the opening portion 35A for contact plug formation is completed and the opening portion 35B for contact plug formation is in the middle of formation, and FIG. 6E shows a state at a time point when formation of the opening portion 35B for contact plug formation is completed. Here, although a resist layer for etching is actually formed, an illustration of such a resist layer is omitted here for the sake of simplicity.
[Process-60]
Next, in order to form contact plugs, a pretreatment for removing a natural oxide film or the like is carried out. FIG. 6F shows a state at a time point when the pretreatment is completed.
[Process-70]
After that time, after a second barrier layer 36 made of Ti (lower layer)/TiN (upper layer) is formed (refer to FIG. 6G), and a tungsten layer is formed over the entire surface of the base 10 by utilizing the blanket tungsten CVD method, the flattening treatment is carried out by utilizing the CMP method. As a result, contact plugs 37A and 37B can be formed within the opening portions 35A and 35B for contact plug formation, respectively (refer to FIG. 6H).